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Lance A. Glasser


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Semiconductor design and manufacturing

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 Smaller Faster Cheaper

© Lance A. Glasser 2007-2010

All Rights Reserved

Craig Barrett used Smaller-Faster-Cheaper as a mantra at Intel for many years.  This is truer today in the semiconductor business than it was even 10 years ago because the preponderance of the customers of the semiconductor industry has shifted from government, as it was in the early days, to industry to, in the last few years, the consumer.  The semiconductor industry provides discretionary trinkets for jaded first-world teenagers, on one hand, and information appliances to the developing masses, on the other.  Semiconductor companies compete on a global scale—Idaho competes with Germany competes with Japan competes with Korea competes with Taiwan competes with China.  There is no shade from the blaze of competition.  Price and margin pressures are enormous, and growing.  

Technology nodes may be lasting a little longer, but the drive for productivity is undiminished.  Moore’s Law is first and foremost a statement about economics rather than an extrapolation of linewidths. As it becomes more difficult to use sub-wavelength lithography to squeeze linewidths, increased productivity and lower costs must come elsewhere. They come in part from innovations in new device geometries and materials.  Indeed, as we continue to march down the roadmap, a greater and greater percentage of the productivity is coming from device rather than lithography innovation.  We feel this in several ways.  For instance, we are seeing an exploding diversity in the number of materials that need to be measured.  It seems that there is an unspoken race to put every non-radioactive material on the periodic table into an integrated circuit.  Hafnium?  Nickel?  Germanium?  Sure.  Another aspect of this is that it is harder to predict the insertion node for new materials and structures than it is to predict linewidth shrinks.  That means that the industry is often surprised by the push out of advanced materials, such as low-k dielectrics, and structures, such as FinFETs.  This has added another layer of business risk.  Power dissipation and leakage current control are other drivers of new materials and more complex 3-D structures with higher aspect ratios.  Note that the Front End Of Line (FEOL: the formation of the transistor) has become more problematic than the Back End Of Line (BEOL: the interconnect), in a reverse from previous years when people struggled with the introduction of copper damascene processes.  

The risk profile that the semiconductor industry lives under is under is towering.  It takes billions of dollars to build factories that turn out parts selling for a few dollars.  These plants burn through about a million dollars an hour.  In this environment, operational excellence is oxygen, without which they cannot survive.  Luckily for inspection and metrology companies, part of this equation is yield maximization at every point in time.  Yield is core to semiconductor companies (which is one of the reasons that yield management consulting is a difficult business—world-class companies do not outsource core competencies.)   On top of this, however, an operationally excellent wafer fab will also try to systematically drive down costs and transfer risks to their vendors.  This is why semiconductor companies often institute dual vendor policies, why they try to commoditize their suppliers, why they demand open standard interfaces, why they are paranoid about their intellectual property, and why they try to minimize queue times and cycle times in their fabs.  If you are in a semiconductor company and yield and operational excellence are not core competencies, you should go fabless.  Eventually you will anyhow.

We are seeing the research and development needed to stay at the leading edge of the semiconductor business increase steadily over the last few years.  This has driven a consolidation of R&D into fewer bleeding edge players. The IBM Alliance is the most famous of these.  The growing expense has also helped drive the increasing importance of cooperative research institutes such as International Sematech, IMEC, and Albany Nanotech.  This same phenomenon has also resulted in increasing buying power for the semiconductor alliances; per Porter’s forces of competition.  

We have seen that the factor of two advantage in speed and cost one traditionally achieved moving from node to the adjacent node is now diminished.  Indeed, if this factor became smaller than one, Moore’s Law would stop.  On top of this, the amount of analog circuitry on an integrated circuit is increasing, and analog circuits do not shrink the same way as digital.  These two factors mean that the advantage of careening from node to node is diminished and, therefore, not all semiconductor companies feel the same compulsion to shrink quickly as they once did.  This is causing an increasing gap between our leading edge wafer fabs and the mainstream.  Older model tools are lasting longer in production.  Together with the rise of the consumer market formfactor, this is also forcing an increased use of system-in-package technology, where each part can be optimized for what the technology does best.

Process control is certainly getting more difficult for wafer fabs as the number of devices on a wafer explode and the criticality of dimensional control becomes more exquisite.  This has led to an increase in single-wafer processing.  No longer are fab factories pipelined systems with a single path from input to output.  Instead we have a combinatoric ravel of paths where tolerance stack ups can happen on any unique route.  This puts pressure on the customer to sample more.  On top of this, in-wafer variations are as big, if not bigger, than wafer-to-wafer variations.  

Another megatrend is the increasing importance of control (e.g., overlay and CD) in lithography.  While the pitch of single-exposure lines and vias are determined by the wavelength of light (in air or in water as appropriate), the linewidth is determined by the tightness of process control.  Nonlinearities, for instance with spacers and etching or with double exposure, can double the spatial frequency of the lithography process.  Such tricks are needed to get down to the pitches required by the 22 nm node and below with 193 nm light, and will undoubtedly be used.  It is ironic, but in some sense, the poorer are the available choices to accomplish a task, the more money is spent on it. Lithography is an increasing fraction of the semiconductor capital budget.  Note that these nonlinear spatial frequency doubling tricks are not available to optical inspection because there is no nonlinearity to exploit on the integrated circuit.

The semiconductor industry continues to claw their way down Moore’s Law and inexorably drive down costs through lithography, through device material and structure innovation, through design, through yield management, through improvements in cycle time and operational excellence, though WIP (work in process), capital, and materials spending control, and through more sophisticated and focused vendor management.  All of these activities are core to their survival.

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